1. Field of the Invention
The present invention relates to structures for clamping a boost signal, and more particularly to a structure for restricting an upper limit of boosting level on a boost signal line such as a word line in a semiconductor memory device.
2. Description of the Background Art
In a semiconductor memory device using a single power supply, a power supply voltage is boosted on-chip to generate a boost signal. Such boost signals serve as a word line driving signal in a DRAM (Dynamic Random Access Memory) and a programming high voltage in EEPROM.
An entire structure of a DRAM is shown in FIG. 12. The DRAM is only an example of applications of the present invention, and the present invention is not necessarily be limited to the DRAM.
Referring to FIG. 12, the DRAM includes a memory cell array 500 in which memory cell MC are arranged in a matrix of rows and columns. In memory cell array 500, a word line WL is arranged corresponding to each row and a pair of bit lines BLP are arranged corresponding to each column. In FIG. 12, one word line WL and one pair of bit lines BLP are represented. Memory cell MC includes a capacitor 42 storing information in a form of electric charges, and a transfer gate 41 being conductive in response to a potential of a signal on word line WL to connect capacitor 42 to a corresponding bit line (BL). Transfer gate 41 is usually structured with an n-channel MOS (insulating gate-type field effect) transistor 41.
The DRAM further includes an address buffer 502 taking in an external multiple-bit address signal A0-An for generating an internal address signal; a row decoder 504 decoding an internal row address signal applied from address buffer 502 for generating a signal designating a corresponding row in memory cell array 500; and a word line driver 506 responsive to the row designating signal applied from row decoder 504 for driving a corresponding row in memory cell array 500 to the selected state. Word line driver 506 transmits a boost signal applied from a boosting circuit 508 on a selected word line (a word line designated by the row designating signal).
The DRAM further includes a column decoder 510 decoding an internal column address signal applied from address buffer 502 for generating a signal designating a corresponding column in memory cell array 500; a sense amplifier sensing and amplifying the data in a selected memory cell in memory cell array 500 (a memory cell connected to the selected word line); and an IO gate connecting a corresponding column to a data input/output terminal DQ via an internal data line in response to the column designating signal applied from column decoder 510. In FIG. 12, the sense amplifier and the IO gate are shown in a block 512.
Boosting circuit 508 generates a signal having a voltage level higher than an operating power supply voltage in response to an activating signal .phi.0 applied from a clock control circuit 514. Clock control circuit 514 generates necessary internal control signals in response to an external row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE. In FIG. 12, clock control circuit 514 is shown supplying the internal control signal to only address buffer 502 and boosting circuit 508.
In operation, address buffer 502 generates internal row and column address signals from multi-bit address signal A0-An. Timings for generating internal row address signal and internal column address signal are given by signals /RAS and /CAS, respectively. Word line driver 506 drives the selected word line in response to the row designating signal from row decoder 504. Accordingly, a potential of selected word line WL rises. In response to the potential rise of word line WL, transfer gate 41 in memory cell MC becomes conductive, capacitor 42 is connected to bit line BL, and a potential of bit line BL changes according to the stored electric charges of capacitor 42. Since no selected memory cell is connected to a complementary bit line /BL, a potential of complementary bit line /BL is at a precharge potential level. The sense amplifier in block 512 then senses and amplifies a potential difference between bit lines BL and /BL.
These bit lines BL and /BL are selected through the IO gate in response to column decoding operation of column decoder 510, so that the data write or read to memory cell MC is carried out. Write enable signal /WE determines which of data write and read is to be carried out.
Boosting circuit 508 generates a boost signal because of the following reason. Transfer gate 41 in memory cell MC is structured by the n-channel MOS transistor. Transfer gate 41 can transmit a voltage of Vcc-Vth level when a potential of word line WL is at an operating power supply voltage Vcc level. Vth represents a threshold voltage of transfer gate 41. Thus, a full Vcc level voltage cannot be stored in capacitor 42. Capacitor 42 can store electric charges Q given by Q=C.multidot.(V-Vcp), where C represents capacitance of capacitor 42, V represents a voltage transmitted through transfer gate 41, and Vcp represents a potential of the other electrode (cell plate) of capacitor 42. Voltage V has to be increased in order to increase the stored electric charges Q of capacitor 42. Thus, boosting circuit 508 generates the boost signal for boosting the potential level of word line WL to a level still higher than operating power supply voltage Vcc level in order to eliminate signal transmission loss in transfer gate 41. Accordingly, a high level voltage Vcc applied on bit line BL is written in capacitor 42.
FIG. 13 is a schematic diagram showing a structure of a conventional boosting circuit. In FIG. 13, boosting circuit includes a boost signal generating circuit 30 generating a boost signal .phi.out from power supply voltage Vcc, and a clamping circuit 60 clamping boost signal .phi.out supplied to a boost line 50 from boost signal generating circuit 30 to a predetermined potential. Boost signal .phi.out on boost line 50 is supplied, for example, to a gate of MOS transistor 41 in an internal circuit 40 serving as a memory cell array. In case of the DRAM, boost signal .phi.out on boost line 50 is transmitted onto the selected word line through the word line driver. In other words, internal circuit 40 is considered to include the word line driver and the memory cell array in the DRAM. Since the boosting circuit in a semiconductor device will be discussed in general in the following, this array portion will be described as the internal circuit.
A voltage level of boost signal .phi.out on boost line 50 is equal to or greater than the sum of threshold voltage Vth and power supply voltage Vcc of MOS transistor 41.
Boost signal generating circuit 30 includes a boost control circuit 31 operating by using power supply voltage Vcc and the ground potential, respectively supplied to a power supply voltage node 10 and a ground potential node 20, as operating power supply voltages, for generating boost control signals .phi.1, .phi.2, and .phi.3 in response to boost activating signal .phi.0; and a booster 32 generating boost signal .phi.out on boost line 50 in response to boost control signals .phi.1 through .phi.3. Booster 32 includes an n-channel MOS transistor 32a connected between power supply voltage node 10 and boost line 50 and responsive to a first boost control signal .phi.1 for connecting power supply voltage node 10 and boost line 50 electrically; a capacitor 32b responsive to second boost control signal .phi.2 for boosting the signal potential on boost line 50 through the capacitive coupling, and an n-channel MOS transistor 32c connected between boost line 50 and ground potential node 20 and responsive to third boost control signal .phi.3 for connecting boost line 50 and ground potential node 20 electrically.
Clamping circuit 60 includes two diode-connected n-channel MOS transistors 61 and 62. Diode-connected n-channel MOS transistors 61 and 62 are serially connected between boost line 50 and power supply voltage node 10 in a forward direction from boost line 50. The operation of the structure shown in FIG. 13 will be described below referring to FIG. 14.
Before time t1, boost activating signal .phi.0 is at the low level ("L"). In this state, boost control signals .phi.1, .phi.2 and .phi.3 generated from boost control circuit 31 are at the low level, the low level, and the high level ("H"), respectively. In booster 32, MOS transistor 32a is turned off, MOS transistor 32c is turned on, and boost line 50 is at the low level. In clamping circuit 60, both MOS transistors 61 and 62 are turned off because they are in the reverse-biased state.
At time t1, when boost activating signal .phi.0 rises to the high level, boost control circuit 31 first renders the third boost control signal to the low level, and raises the first boost control signal .phi.1 to the high level for a predetermined period. Consequently, MOS transistor 32a is turned on and MOS transistor 32c is turned off, and boost line 50 is charged to the level of (Vcc-Vth) via MOS transistor 32a. Vth indicates the threshold voltage of transistor 32a. In the following description, the threshold voltage of MOS transistors 32a, 32c, 61, and 62 are all assumed to be Vth, unless otherwise mentioned.
At time t2, first boost control signal .phi.1 falls to the low level, and MOS transistor 32a is turned off. Boost line 50 is in an electrically floating state at the voltage level of (Vcc-Vth). At this time, the second boost control signal .phi.2 rises to the high level and the voltage level of boost line 50 increases by capacitor 32b. When boost signal .phi.out on boost line 50 is higher than the voltage level of (Vcc+2Vth), MOS transistors 62 and 61 are turned on, causing boost line 50 electrically connected to power supply voltage node 10. More particularly, voltage .phi.out of boost line 50 is clamped at the voltage level of (Vcc+2Vth) as shown in FIG. 14 at (e).
In response to the boost signal of boost line 50, transistor 41 becomes conductive for transmitting the signal at power supply voltage Vcc level without signal loss into internal circuit 40.
At time t3, when boost activating signal .phi.0 falls to the low level, second boost control signal .phi.2 falls to the low level and third boost control signal .phi.3 rises to the high level. Consequently, MOS transistor 32c is turned on and boost line 50 is discharged to ground potential node 20 via MOS transistor 32c, causing boost signal .phi.out to be at the low level (threshold voltage Vth level).
Clamping circuit 60 prevents the generation of the boost signal having an unduly high voltage level.
In a semiconductor integrated circuit device such as a semiconductor memory device, a transistor serving as a component is made smaller for higher density and higher integration and a breakdown voltage of the transistor is decreased. In order to keep the reliability of elements, the power supply voltage is required to be reduced. However, the semiconductor memory devices is not used singly, but serves as a component of a system. A logic IC, such as a processor, has not been processed so much finely as the semiconductor memory device. The system power supply voltage is determined by the power supply voltage of the IC, such as TTL. In order to construct a single power supply system, in the semiconductor memory device, an external power supply voltage is down-converted internally so as to generate a down-converted operating power supply voltage for driving internal circuitry. For example, using an external power supply voltage extVcc of 5 V, 3.3 V of internal power supply voltage intVcc is generated by a voltage-down converter provided internally. An example of a semiconductor device having such a dual power supply voltage is disclosed in "Dual Operating Voltage Scheme--Single 5 V 16M bit DRAM" written by Horiguchi et al., IEEE, Journal of Solid-State Circuits, Vol. 23, No. 5, October, 1988.
Threshold voltage Vth of the MOS transistor can be obtained by flat band voltage VFB, Fermi level .phi.F, a capacitance Cox per unit area of a gate insulating film and a charge amount induced at a channel surface as follows: EQU Vth=VFB+2.multidot..phi.F-(QD/Cox)
More particularly, since the scaling rule cannot apply to threshold voltage Vth, the threshold voltage is not scaled down in response to the fine processing of the transistor, unlike the power supply voltage. Also, since a back gate voltage (a substrate bias voltage) is applied to the MOS transistor, an absolute value of the threshold voltage is increased. As to threshold voltage Vth of this n-channel MOS transistor, for example, that of a transistor of a 0.5 .mu.m design rule is 1.7 V.
When the boosting circuit shown in FIG. 13 is employed for boosting a word line in a 16M-bit DRAM by utilizing transistors of a 0.5 .mu.m design rule, the internal power supply voltage (internal down-converted voltage) intVcc is used as power supply voltage Vcc. Burn-in test is one of the reliability determination tests of the DRAM. In the burn-in test, initial failure due to particles are removed by applying a power supply voltage higher than the power supply voltage usually used. Screening of initial failure is carried out. When 6 V is applied as internal power supply voltage intVcc in burn-in test of the DRAM, boosting voltage .phi.out of boost line 50 during boosting is expressed as follows: EQU Vcc+2.multidot.Vth=6+2.multidot.1.7=9.4 V
Since -3 V is applied as substrate bias voltage Vpp, 9.4-(-3)=12.4 V is applied, for example, across a PN junction (a junction between a substrate and a source/drain region) of n-channel MOS transistor 32c in booster 32. Since the junction breakdown voltage of the transistor is 12 V, reliability of the transistor is impaired. In order to avoid such a problem, possible consideration is to reduce power supply voltage Vcc during the burn-in test. However, when power supply voltage Vcc during the burn-in test is reduced, time taken for the burn-in test will be longer. Especially in a semiconductor integrating circuit device including an internal power supply voltage-down converter within the chip, the period of the burn-in test is necessarily long because internal power supply voltage intVcc lower than external power supply voltage extVcc is used as power supply voltage Vcc. If power supply voltage Vcc during the burn-in test is further reduced, time taken for burn-in test will be still longer.
Such problem regarding boosting voltage can be found not only in the burn-in test, but also in the acceleration test such as life test.